The present disclosure generally relates to memory devices and, more particularly, to memory modules (e.g., sub-systems) implemented with dedicated processing circuitry, as well as memory devices.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Generally, a computing system includes processing circuitry (e.g., one or more processors) and memory devices (e.g., chips or integrated circuits). Often, one or more memory devices may be implemented on a memory module, such as a dual in-line memory module (DIMM), to store data accessible to the processing circuitry. For example, based on a user input to the computing system, the processing circuitry may request and a memory module may retrieve corresponding data from its memory devices. In some instances, the retrieved data may include instructions executable by the processing circuitry to perform an operation and/or data to be input to the operation. Additionally, in some instances, data output (e.g., resulting) from the operation may be stored in memory, for example, to enable subsequent retrieval.
In any case, at least in some instances, multiple operations may be targeted for performance by the processing circuitry, for example, over the same or overlapping time periods. As such, processing power (e.g., capabilities) of the processing circuitry may be allocated (e.g., shared or divided) between performance of the various operations. Even as processing power continues to increase, at least in some instances, centralizing processing in the main processing circuitry of a computing system may limit operational efficiency of the computing system, for example, with respect to latency of operation performance.